Asynchronous Early Output Dual-bit Full Adders Based on Homogeneous and Heterogeneous Delay-insensitive Data Encoding

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aut.relation.endpage73
aut.relation.journalWSEAS Transactions on Circuits and Systemsen_NZ
aut.relation.pages10
aut.relation.startpage64
aut.relation.volume16en_NZ
aut.researcherPrasad, Krishnamachar
dc.contributor.authorBalasubramanian, Pen_NZ
dc.contributor.authorPrasad, Ken_NZ
dc.date.accessioned2017-07-26T23:47:02Z
dc.date.available2017-07-26T23:47:02Z
dc.date.copyright2017-04-25en_NZ
dc.date.issued2017-04-25en_NZ
dc.description.abstractThis paper presents the designs of asynchronous early output dual-bit full adders without and with redundant logic (implicit) corresponding to homogeneous and heterogeneous delay-insensitive data encoding. For homogeneous delay-insensitive data encoding only dual-rail i.e. 1-of-2 code is used, and for heterogeneous delay-insensitive data encoding 1-of-2 and 1-of-4 codes are used. The 4-phase return-to-zero protocol is used for handshaking. To demonstrate the merits of the proposed dual-bit full adder designs, 32-bit ripple carry adders (RCAs) are constructed comprising dual-bit full adders. The proposed dual-bit full adders based 32-bit RCAs incorporating redundant logic feature reduced latency and area compared to their non-redundant counterparts with no accompanying power penalty. In comparison with the weakly indicating 32-bit RCA constructed using homogeneously encoded dual-bit full adders containing redundant logic, the early output 32-bit RCA comprising the proposed homogeneously encoded dual-bit full adders with redundant logic reports corresponding reductions in latency and area by 22.2% and 15.1% with no associated power penalty. On the other hand, the early output 32-bit RCA constructed using the proposed heterogeneously encoded dual-bit full adder which incorporates redundant logic reports respective decreases in latency and area than the weakly indicating 32-bit RCA that consists of heterogeneously encoded dual-bit full adders with redundant logic by 21.5% and 21.3% with nil power overhead. The simulation results obtained are based on a 32/28nm CMOS process technology.
dc.identifier.citationWSEAS Transactions on Circuits and Systems, Volume 16, pp. 64-73
dc.identifier.issn1109-2734en_NZ
dc.identifier.issn2224-266Xen_NZ
dc.identifier.urihttps://hdl.handle.net/10292/10696
dc.publisherWorld Scientific and Engineering Academy and Societyen_NZ
dc.relation.urihttp://wseas.org/wseas/cms.action?id=14937en_NZ
dc.rightsThe articles can be uploaded in libraries and institutional repository as long as they properly cite the articles according to the publisher.
dc.rights.accessrightsOpenAccessen_NZ
dc.subjectAsynchronous design; Digital circuits; Full adder; Ripple carry adder; Indication; Early output; Standard cells; CMOS
dc.titleAsynchronous Early Output Dual-bit Full Adders Based on Homogeneous and Heterogeneous Delay-insensitive Data Encodingen_NZ
dc.typeJournal Article
pubs.elements-id279295
pubs.organisational-data/AUT
pubs.organisational-data/AUT/Design & Creative Technologies
pubs.organisational-data/AUT/Design & Creative Technologies/Engineering, Computer & Mathematical Sciences
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