Early Output Hybrid Input Encoded Asynchronous Full Adder and Relative-timed Ripple Carry Adder

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aut.relation.endpage65
aut.relation.pages4
aut.relation.startpage62
aut.researcherPrasad, Krishnamachar
dc.contributor.authorBalasubramanian, Pen_NZ
dc.contributor.authorPrasad, Ken_NZ
dc.contributor.editorArabnia, HRen_NZ
dc.contributor.editorDeligiannidis, Len_NZ
dc.date.accessioned2018-10-22T23:50:13Z
dc.date.available2018-10-22T23:50:13Z
dc.date.copyright2016-07-25en_NZ
dc.date.issued2016-07-25en_NZ
dc.description.abstractThis paper presents a new early output hybrid input encoded asynchronous full adder designed using dual-rail and 1-of-4 delay-insensitive data codes. The proposed full adder when cascaded to form a ripple carry adder (RCA) necessitates the use of a small relative-timing assumption with respect to the internal carries, which is independent of the RCA size. The forward latency of the proposed hybrid input encoded full adder based RCA is data-dependent while its reverse latency is the least equaling the propagation delay of just one full adder. Compared to the best of the existing hybrid input encoded full adders based 32-bit RCAs, the proposed early output hybrid input encoded full adder based 32-bit RCA enables respective reductions in forward latency and area by 7.9% and 5.6% whilst dissipating the same average power; in terms of the theoretically computed cycle time, the latter reports a 10.9% reduction compared to the former.
dc.identifier.citationIn Proceedings of the 14th International Conference on Embedded Systems, Cyber-physical Systems, and Applications, pp. 62-65, July 25-28, 2016, Las Vegas, USA.en_NZ
dc.identifier.isbn1-60132-433-2en_NZ
dc.identifier.urihttps://hdl.handle.net/10292/11900
dc.publisherCSREA Pressen_NZ
dc.relation.urihttps://worldcomp.org/events/2016/program/esc_icm_27
dc.rightsNOTICE: this is the author’s version of a work that was accepted for publication. Changes resulting from the publishing process, such as peer review, editing, corrections, structural formatting, and other quality control mechanisms may not be reflected in this document. Changes may have been made to this work since it was submitted for publication. A definitive version was subsequently published in (see Citation). The original publication is available at (see Publisher's Version).
dc.rights.accessrightsOpenAccessen_NZ
dc.subjectAsynchronous design; Relative-timing; Indication; Ripple Carry Adder (RCA); CMOS; Standard cells
dc.titleEarly Output Hybrid Input Encoded Asynchronous Full Adder and Relative-timed Ripple Carry Adderen_NZ
dc.typeConference Contribution
pubs.elements-id208715
pubs.organisational-data/AUT
pubs.organisational-data/AUT/Design & Creative Technologies
pubs.organisational-data/AUT/Design & Creative Technologies/School of Engineering
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