Low power self-timed carry lookahead adders
aut.conference.type | Paper Published in Proceedings | |
aut.relation.endpage | 460 | |
aut.relation.pages | 4 | |
aut.relation.startpage | 457 | |
aut.researcher | Prasad, Krishnamachar | |
dc.contributor.author | Balasubramanian, P | |
dc.contributor.author | Dhivyaa, D | |
dc.contributor.author | Jayakirthika, JP | |
dc.contributor.author | Kaviyarasi, P | |
dc.contributor.author | Prasad, K | |
dc.date.accessioned | 2013-08-13T20:48:53Z | |
dc.date.accessioned | 2013-08-13T21:56:04Z | |
dc.date.available | 2013-08-13T20:48:53Z | |
dc.date.available | 2013-08-13T21:56:04Z | |
dc.date.copyright | 2013-08-04 | |
dc.date.issued | 2013-08-04 | |
dc.description.abstract | Cell based self-timed synthesis of recursive carry lookahead adders (RCLA) utilizing generate, propagate and kill functions is described in this paper, and are compared with the recently proposed designs of self-timed section-carry based carry lookahead (SCBCLA) adders. From the simulation results corresponding to a 130nm CMOS process, it is found that with 2-bit CLA, the RCLA adder dissipates 20.2% less power than the SCBCLA adder. With 4-bit CLA, the RCLA adder reports power reduction by 16.5% than the SCBCLA adder. Further, for addition widths ranging from 32 to 64-bits, RCLA adders consume 19% less average power compared to SCBCLA adders. | |
dc.identifier.citation | 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS 2013) held at Ohio State University, Columbus, Ohio, Columbus, Ohio, USA, 2013-08-04to 2013-08-07, pp.457 - 460 (4) | |
dc.identifier.uri | https://hdl.handle.net/10292/5603 | |
dc.publisher | IEEE | |
dc.relation.isreplacedby | 10292/5608 | |
dc.relation.isreplacedby | http://hdl.handle.net/10292/5608 | |
dc.relation.replaces | http://hdl.handle.net/10292/5602 | |
dc.relation.replaces | 10292/5602 | |
dc.relation.uri | http://www.epapers.org/mwscas2013/ESR/paper_details.php?PHPSESSID=gpblo8fern0d9dcpnrbcu8l921&paper_id=8184 | |
dc.rights | Copyright © 2013 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | |
dc.rights.accessrights | OpenAccess | |
dc.subject | Self-timed | |
dc.subject | Quasi-delay-insensitive | |
dc.subject | Logic synthesis | |
dc.subject | Standard cells | |
dc.subject | Carry lookahead | |
dc.subject | Low power | |
dc.title | Low power self-timed carry lookahead adders | |
dc.type | Conference Contribution | |
pubs.elements-id | 153175 | |
pubs.organisational-data | /AUT | |
pubs.organisational-data | /AUT/Design & Creative Technologies | |
pubs.organisational-data | /AUT/Design & Creative Technologies/School of Engineering |