Latency Optimized Asynchronous Early Output Ripple Carry Adder Based on Delay-insensitive Dual-rail Data Encoding
aut.relation.endpage | 74 | |
aut.relation.journal | INTERNATIONAL JOURNAL OF CIRCUITS, SYSTEMS AND SIGNAL PROCESSING | en_NZ |
aut.relation.pages | 10 | |
aut.relation.startpage | 65 | |
aut.relation.volume | 11 | en_NZ |
aut.researcher | Prasad, Krishnamachar | |
dc.contributor.author | Balasubramanian, P | en_NZ |
dc.contributor.author | Prasad, K | en_NZ |
dc.date.accessioned | 2019-02-17T22:58:39Z | |
dc.date.available | 2019-02-17T22:58:39Z | |
dc.date.copyright | 2017-06-14 | en_NZ |
dc.date.issued | 2017-06-14 | en_NZ |
dc.description.abstract | Asynchronous circuits employing delay-insensitive codes for data representation i.e. encoding and following a 4-phase return-to-zero protocol for handshaking are generally robust. Depending upon whether a single delay-insensitive code or multiple delay-insensitive code(s) are used for data encoding, the encoding scheme is called homogeneous or heterogeneous delay-insensitive data encoding. This article proposes a new latency optimized early output asynchronous ripple carry adder (RCA) that utilizes single-bit asynchronous full adders (SAFAs) and dual-bit asynchronous full adders (DAFAs) which incorporate redundant logic and are based on the delay-insensitive dual-rail code i.e. homogeneous data encoding, and follow a 4-phase return-to-zero handshaking. Amongst various RCA, carry lookahead adder (CLA), and carry select adder (CSLA) designs, which are based on homogeneous or heterogeneous delayinsensitive data encodings which correspond to the weak-indication or the early output timing model, the proposed early output asynchronous RCA that incorporates SAFAs and DAFAs with redundant logic is found to result in reduced latency for a dualoperand addition operation. In particular, for a 32-bit asynchronous RCA, utilizing 15 stages of DAFAs and 2 stages of SAFAs leads to reduced latency. The theoretical worst-case latencies of the different asynchronous adders were calculated by taking into account the typical gate delays of a 32/28nm CMOS digital cell library, and a comparison is made with their practical worst-case latencies estimated. The theoretical and practical worst-case latencies show a close correlation. The proposed early output 32-bit asynchronous RCA, which contains 2 stages of SAFAs in the least significant positions and 15 stages of DAFAs in the more significant positions, reports the following optimizations in latency over its architectural counterparts for a similar adder size: i) 35.3% reduction in latency over a weakindication section-carry based CLA (SCBCLA), ii) 30.5% reduction in latency over a weak-indication hybrid SCBCLA-RCA, iii) 20.2% reduction in latency over an early output recursive CLA (RCLA), iv) 18.7% reduction in latency over an early output hybrid RCLA-RCA, and v) a 13% reduction in latency over an early output CSLA that features an optimum 8-8-8-8 uniform input partition. | |
dc.identifier.citation | International Journal of Circuits, Systems and Signal Processing, Vol. 11, pp. 65-74. | |
dc.identifier.uri | https://hdl.handle.net/10292/12252 | |
dc.publisher | North Atlantic University Union (NAUN) | |
dc.relation.uri | http://www.naun.org/main/NAUN/circuitssystemssignal/2017/a162005-aaz.pdf | en_NZ |
dc.rights | The PDF files of all NAUN Journals are open to everyone, without any username/password requirements. | |
dc.rights.accessrights | OpenAccess | en_NZ |
dc.subject | Asynchronous design; Digital circuits; Single-bit full adder; Dual-bit full adder; Ripple carry adder; Indication; Early output; Standard cells; CMOS | |
dc.title | Latency Optimized Asynchronous Early Output Ripple Carry Adder Based on Delay-insensitive Dual-rail Data Encoding | en_NZ |
dc.type | Journal Article | |
pubs.elements-id | 281541 | |
pubs.organisational-data | /AUT | |
pubs.organisational-data | /AUT/Design & Creative Technologies | |
pubs.organisational-data | /AUT/Design & Creative Technologies/Engineering, Computer & Mathematical Sciences |
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