Implementation of high speed image filtering in a novel FPGA-based system
| aut.embargo | No | en_NZ |
| dc.contributor.advisor | Hosseini, Hamid Gholam | |
| dc.contributor.author | Hu, Shuying | |
| dc.date.accessioned | 2018-03-08T03:27:30Z | |
| dc.date.available | 2018-03-08T03:27:30Z | |
| dc.date.copyright | 2006 | |
| dc.date.issued | 2006 | |
| dc.description.abstract | Real-time image and video processing is becoming increasingly important in many applications. A high speed image processing system involves grabbing images from a single or multiple sensors and processing of the data in a limited time. Therefore, the requirement of real-time processing of the images is become the key problem in dealing with such applications. Moreover, to obtain the best performance, it is vital that algorithms and hardware of a high speed image processing system to be reconfigurable and flexible. This thesis proposes a new mechanism to increase image processing speed using Field Programmable Gate Array (FPGA) technology. It also presents a new design method of combining software design, using high level language C/C++, with hardware design, using hardware description language VHDL, in FPGAs. The mixed hardware/software method utilises the advantages of both hardware and software methods. Moreover, the ability to compile software algorithms directly for the FPGAs makes them more efficient for less cost, and low risk applications. The proposed system consists of one core processor for the software design part and some functional units for the hardware design part. The core processor controls and communicates with the functional units. Each functional unit serves one special data or image channel by performing high speed sampling and pre-processing functions. These functions are basically simple, iterated and suitable to be implemented in FPGAs. The core processor can be developed using the high level language C/C++. The functional units can be programmed using VHDL/System C. The whole system can be implemented in an FPGA device. For this project, the Altera Nios Cyclone EP1C20 development board is used. It was found that the new mechanism processes the selected grey scale images at speed of at least 80 times faster than the direct software based methods. | en_NZ |
| dc.identifier.uri | https://hdl.handle.net/10292/11424 | |
| dc.language.iso | en | en_NZ |
| dc.publisher | Auckland University of Technology | |
| dc.rights.accessrights | OpenAccess | |
| dc.subject | Field programmable gate arrays | en_NZ |
| dc.subject | Image processing -- Digital techniques | en_NZ |
| dc.title | Implementation of high speed image filtering in a novel FPGA-based system | en_NZ |
| dc.type | Thesis | en_NZ |
| thesis.degree.grantor | Auckland University of Technology | |
| thesis.degree.name | Master of Engineering (Electrical and Electronic) | en_NZ |