An Optimized Hardware System on Chip for a Support Vector Machine Classifier: a Case Study on Melanoma Detection
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Support Vector Machine (SVM) is a robust machine learning model used for efficient classification with high accuracy. SVM is widely utilized for online classification in various embedded applications. However, implementing the SVM classification algorithm for an embedded system or application is challenging, due to intensive and complicated computations required. This increases the importance of implementing SVM on hardware platforms for achieving high performance computing at low cost and power consumption. Field-Programmable Gate Array (FPGA) is a powerful parallel processing reconfigurable device that is widely used for achieving essential performance of embedded systems, while effectively utilizing hardware resources, offering low cost and low power consumption. Accordingly, FPGA is a promising hardware platform for implementing an efficient embedded SVM classification system, while achieving vital embedded system constraints. SVM has shown high accuracy for classifying melanoma (skin cancer) clinical images within a computer-aided diagnosis system used by dermatologists to detect melanoma early and save lives. This research aims to develop an optimized FPGA-based SVM classifier to be embedded within a low-cost handheld medical scanning device that runs an embedded SVM-based diagnosis system dedicated to early detection of melanoma in primary care. We aim to consider meeting significant constraints of embedded systems, while achieving efficient classification with high accuracy rate. A hardware/software co-design for implementing an SVM classifier onto FPGA is proposed to realize melanoma detection on a chip. This SVM implementation achieves efficient melanoma classification on a recent FPGA-based hybrid platform “Zynq SoC” designed using the latest UltraFast High-Level Synthesis design methodology. The hardware implementation results demonstrate classification accuracy of 97.9% and a significant hardware acceleration rate of up to 37x with only 2.7% resource utilization and 1.69 watts for power consumption. Furthermore, a scalable multi-core architecture is proposed to achieve multi-purpose classification on a single chip/device, which has been validated with a 2-stage cascade classifier implementation with accuracies of 98 % and 73%, to enhance melanoma detection. A simple hardware-friendly design is proposed for the building SVM core of the multi-core architecture, aiming to reduce hardware complexity and optimize implementation results for achieving an efficient classification performance. A novel dynamic hardware system is also proposed for implementing a cascade SVM classifier on FPGA for early melanoma detection. The hardware implementation results are optimized by using the powerful dynamic partial reconfiguration technology, where very low resource utilization of 1% slices and power consumption of 1.5 watts are achieved. The implemented SVM classification systems on Zynq SoC using the proposed hardware designs have shown the least power consumption results among other related implementations, in addition to significantly low hardware resource utilization and processing time with significant speedups and high classification accuracy rates at low cost. Consequently, the implemented Zynq systems meet crucial embedded system constraints of high performance and low cost, resource utilization and power consumption, while achieving efficient classification with high classification accuracy, which promises realization of a cost- and energy-efficient handheld medical scanning device for early detection of melanoma.