Low power self-timed carry lookahead adders
Low power self-timed carry lookahead adders
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Date
2013-08-04
Authors
Balasubramanian, P
Dhivyaa, D
Jayakirthika, JP
Kaviyarasi, P
Prasad, K
Supervisor
Item type
Conference Contribution
Degree name
Journal Title
Journal ISSN
Volume Title
Publisher
IEEE
Abstract
Cell based self-timed synthesis of recursive carry lookahead adders (RCLA) utilizing generate, propagate and kill functions is described in this paper, and are compared with the recently proposed designs of self-timed section-carry based carry lookahead (SCBCLA) adders. From the simulation results corresponding to a 130nm CMOS process, it is found that with 2-bit CLA, the RCLA adder dissipates 20.2% less power than the SCBCLA adder. With 4-bit CLA, the RCLA adder reports power reduction by 16.5% than the SCBCLA adder. Further, for addition widths ranging from 32 to 64-bits, RCLA adders consume 19% less average power compared to SCBCLA adders.
Description
Keywords
Self-timed , Quasi-delay-insensitive , Logic synthesis , Standard cells , Carry lookahead , Low power
Source
2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS 2013) held at Ohio State University, Columbus, Ohio, Columbus, Ohio, USA, 2013-08-04to 2013-08-07, pp.457 - 460 (4)
DOI
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