|dc.description.abstract||The flourish of wireless communications brings along an ever-increasing number of wireless standards. This necessitates software-defined radio (SDR) to implement most transceiver components in the software domain. Ideally, an SDR receiver architecture should achieve a wide frequency dynamic range, low power consumption, high image rejection ratio (IRR), acceptable third-order intercept point (IIP3), and good conversion gain (CG) while maintaining a low noise figure (NF). However, the existing architectures cannot maintain good trade-offs among these performance parameters and doesn’t have wide tuning range. Despite the rapid development of SDRs, it is challenging to realize several components in the software, including antenna, low noise amplifier (LNA), and mixers. This thesis focuses on the design and analysis of reconfigurable downconversion mixers.
The first objective of this thesis was to develop a wideband reconfigurable mixer that attained high CG, low NF, and IRR while maintaining a good trade-off among other performance parameters. To achieve this, we proposed a 0.9-13.5 GHz I/Q, inductively-peaked gm-boosting Gilbert mixer. For the entire band of operation, the mixer attained a good return loss, |S11| of <- 10 dB, CG of 22 dB, NF of 2.5 dB, maximum IRR of 30.2 dB, and an IIP3 of -3.28 dBm, respectively. Additionally, the proposed mixer showed good reliability performance; however, it covered a large die area and attained poor linearity. Thus, a 1.8-5 GHz current bleeding, current mirror balanced mixer was proposed to overcome these problems. The proposed mixer achieved a maximum CG of 18.32 dB, an IIP3 of -5.89 dBm, and a NF of 1.19 dB at 5 GHz. Additionally, the mixer consumed only 10 mW of DC power and covered a 0.32 mm^2 area. However, this design also attained poor IIP3. Thus, a low-power, active inductor-based CMOS down-conversion mixer was proposed. For 0.9-7 GHz, the mixer consumed 12.52 mW and achieved a |S11| of -27.69 dB and a maximum CG of 30.35 dB at the operating frequency. Additionally, the mixer was highly reliable and achieved an excellent IIP3 of 47.4 dBm and a NF of 3.5 dB. The next objective was to check the feasibility of the proposed mixer within the receiver architecture. Thus, we proposed a 0.9-20 GHz, highly reconfigurable I/Q receiver architecture that covered a design area of 4 mm2 and consumed 320 mW of power from a 1.2V supply. The receiver attained an excellent IIP3 of 32 dBm with a NF of 5 dB and a maximum CG of 22.9 dB at 20 GHz.
To further improve the overall performance of our proposed reconfigurable mixers and receivers, we considered evolutionary algorithms (EAs) such as particle swarm optimization (PSO). Upon applying PSO, significant improvement in terms of CG, NF, IIP3, and IRR was achieved compared to the simulated results. Altogether, proposed mixer designs and reconfigurable receiver architecture contribute significantly to the development of SDRs, which will facilitate the deployment of pervasive Internet of Things (IoT) beyond the fifth generation (B5G) or the sixth generation (6G) of wireless communications.||en_NZ