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  •   Open Research
  • AUT Faculties
  • Faculty of Design and Creative Technologies (Te Ara Auaha)
  • School of Engineering, Computer and Mathematical Sciences - Te Kura Mātai Pūhanga, Rorohiko, Pāngarau
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Hardware Implementations of SVM on FPGA: A State-of-the-Art Review of Current Practice

Afifi, SM; Gholamhosseini, H; Poopak, S
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http://hdl.handle.net/10292/10369
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Abstract
The

Support Vector Machine (SVM) is a common machine

learning tool that is

widely used because of its high classification

accuracy

. Implementing SVM for embedded real

-time

applications is very challenging because of the intensi

ve

computations required. This

in creases the

attractiveness

of

implementing SVM on hardware platforms for reaching high

performance computing

with low cost and power consumption.

This paper provides

the

first comprehensive survey of

current

literature (2010-

2015)

of

different hardware implementation

s of

SVM classifier on

Field

-Programmable Gate Array

(FPGA

).

A classification of existing techniques is presented, along with a

critical analysis and

discussion

. A challenging trade

-off between

meeting embedded

real

-time

systems constraints

and

high

classification

accuracy

has been observed.

Finally

, some

key

future research directions

are

suggested.
Keywords
SVM; FPGA; Hardware implementation; Embedded systems; Image processing
Date
November 2015
Source
International Journal of Innovative Science, Engineering & Technology, vol.2(11), pp.733 - 752 (20)
Item Type
Journal Article
Publisher
International Journal of Innovative Science Engineering and Technology (IJISET)
Publisher's Version
http://ijiset.com/articlesv2/articlesv2s11.html
Rights Statement
The authors confirms that “International Journal of Innovative Science, Engineering and Technology” and its Editors, Chief Editor, or reviewers can publish the article online as open access and authors grant permission to edit or alter the article if necessary.

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